This invention relates to microelectronic devices and fabrication methods therefor, and more particularly to microelectronic vertical field effect transistors and fabrication methods therefor.
Field Effect Transistors (FET), also referred to as Metal Oxide Semiconductor Field Effect Transistors (MOSFET) or Complementary Metal Oxide Semiconductor (CMOS) transistors, are widely used in integrated circuit devices including logic, memory and/or microprocessor devices that are used in consumer and/or industrial applications. As the integration density of integrated circuit field effect transistors continues to increase, it may be desirable to continue to shrink the dimensions of the field effect transistors. For example, present day FETs may be fabricated with a minimum device feature size of about 0.18 to about 0.25 xcexcm. However, The International Roadmap for Semiconductors, published by International SEMATECH at http://www.itrs.net/1999_SIA_Roadmap/Home.htm, predicts that the minimum gate length will reach 35 nm in 10-15 years.
Conventionally, features of integrated circuit FETs may be formed on a microelectronic substrate, such as silicon semiconductor substrate, using photolithography and etching. Unfortunately, as the minimum feature size scales into the sub-0.1 xcexcm region, it may be increasingly difficult to define such small features using traditional lithography and etching. Although improved nano-lithography techniques may be developed, it still may be difficult to reliably define features as small as 35 nm or smaller in a controllable and cost-effective way using lithography, to allow mass production. Moreover, from a device physics point of view, as the dimensions of FETs continues to shrink, the suppression of short channel effects may become increasingly difficult.
In attempts to reduce short channel effects, planar fully depleted ultra-thin body Semiconductor-On-Insulator (SOI) FETs have been developed. For example, using a semiconductor-on-insulator substrate and etchback or oxide thinning, ultra-thin SOI channels may be obtained. See, for example, Choi et al., Ultra-Thin Body SO MOSFET for Deep-Sub-Tenth Micron Era, Paper 3.7.1, IEDM, 1999, pp. 919-921. Other approaches have deposited a thin layer of amorphous silicon or silicon germanium alloy on a planar oxide surface, followed by lateral solid-state crystallization. See, Yeo et al., Nanoscale Ultra-Thin-Body Silicon-On-Insulator P-MOSFET with a SiGe/Si Heterostructure Channel, IEEE Electron Device Letters, Vol. 21, No. 4, 2000, pp. 161-163. Unfortunately, although planar fully depleted ultra-thin body devices may be capable of reducing short channel effects, it may be difficult to further increase the integration density and/or performance of these devices, because the gate may still be defined by lithography.
Double gate and/or surround gate FETs also have been proposed to reduce short channel effects. A double/surround gate FET may include a thin channel that is controlled by both a front gate and a back gate. Short channel effects may be suppressed because the two gates can be effective in terminating drain field lines and preventing the drain potential from impacting the source. Double gate devices may be extended to provide surround gate devices in which the gate wraps around the channel. As shown by computer simulations, in order to effectively suppress the short channel effects in a double gate MOSFET, the channel thickness may need to be as thin as one-half to one-third of the gate length. See, for example, Wong et al., Device Design Considerations for Double-Gate, Ground-plane, and Single-Gated Ultra-Thin SOI MOSFET""s at the 25 nm Channel Length Generation, IEDM, 1998, pp. 407-410.
FETs including double/surround gate FETs may be grouped into two categories based on the channel orientation. In horizontal devices, carrier conduction from source to drain through the channel occurs in a direction that is generally parallel to the face of the microelectronic substrate. In contrast, in vertical devices, carrier conduction from source to drain through the channel occurs in the vertical direction, generally orthogonal to the face of the microelectronic substrate.
In horizontal approaches for fabricating double/surround gate FETs, the gate length may be defined by lithography, and the formation of a back gate beneath the thin channel and its accurate alignment to the top gate may present challenges. See, for example, the publications to Tanaka et al., entitled Ultrafast Operation of Vth-Adjusted p+-n+ Double-Gate SOI MOSFETs, IEEE Electron Device Letters. Vol. 15, No. 10, October 1994, pp. 386-388; Colinge et al., entitled Silicon-on-Insulator xe2x80x9cGate-All-Around Devicexe2x80x9d, IEDM, 1990, pp. 595-598; Leobandung et al., entitled Wire-Channel and Wrap-Around-Gate Metal-Oxide-Semiconductor Field-Effect Transistors With a Significant Reduction of Short Channel Effects, Journal of Vacuum Science Technology B, 15(6), November/December 1997, pp. 2791-2794; Hisanoto et al., entitled A Folded-Channel MOSFET for Deep-sub-tenth Micron Era, IEDM, 1998, pp. 1032-1034; and Lee et al., entitled Super Self-Aligned Double-Gate (SSDG) MOSFETs Utilizing Oxidation Rate Difference and Selective Epitaxy, IEDM, 1999, pp. 71-74.
In contrast, in vertical devices, the fabrication of the double/surround gate structures may be more straightforward because both the front and back gates can be formed simultaneously. Vertical FETs also may be fabricated with a higher integration density, because carrier conduction occurs orthogonal to the substrate face. See, Takato et al., entitled High Performance CMOS Surrounding Gate Transistor (SGT) for Ultra High Density LSIs, IEDM, 1988, pp. 222-225; Risch et al., entitled Vertical MOS Transistors With 70 nm Channel Length, IEEE Transactions on Electron Devices, Vol. 43, No. 9, September 1996, pp. 1495-1498; Auth et al., entitled Scaling Theory for Cylindrical, Fully-Depleted, Surrounding-Gate MOSFET""s, IEEE Electron Device Letters, Vol. 18, No. 2, February 1997, pp. 74-76; and Yang et al., entitled 25-nm p-Channel Vertical MOSFET""s With SiGeC Source-Drains, IEEE Electron Device Letters, Vol. 20, No. 6, June 1999, pp. 301-303. In vertical devices, the gate length is usually defined by thin-film deposition. However, the lithography actually may be more difficult, because the channel thickness, which may be about one-third of the gate length, generally is lithography-dependent.
A vertical replacement gate MOSFET also is described in a publication by Hergenrother et al., entitled The Vertical Replacement-Gate (VRG) MOSFET: A 50 nm Vertical MOSFET With Lithography-Independent Gate Length, IEDM, 1999, p. 75, the disclosure of which is hereby incorporated herein by reference in its entirety. As described in the abstract of Hergenrother et al., the VRG MOSFET is the first MOSFET ever built that combines 1) a gate length controlled precisely through a deposited film thickness, independently of lithography and etch, and 2) a high-quality gate oxide grown on a single-crystal Si channel. In addition to this unique combination, the VRG-MOSFET includes a self-aligned S/D formed by solid source diffusion (SSD) and small parasitic overlap, junction, and S/D capacitances. The drive current per xcexcm of coded width is significantly higher than that of advanced planar MOSFETs because each rectangular device pillar (with a thickness of minimum lithographic dimension) contains two MOSFETs driving in parallel. All of this is achieved using current manufacturing methods, materials, and tools, and competitive devices with 50-nm gate lengths (LG) having been demonstrated without advanced lithography. See the Hergenrother et al. abstract.
As also described in the xe2x80x9cDevice Fabricationxe2x80x9d section of Hergenrother et al., in the VRG process, arsenic was implanted into an epi Si wafer to form the device drain and a thin oxide diffusion barrier was deposited. A PSG/nitride/undoped oxide/nitride/PSG/nitride stack was deposited and a trench (or window) with nearly vertical sidewalls was etched through the entire stack. The boron-doped epitaxial Si device channel was grown selectively in this trench and the channel was planarized to the top nitride layer by CMP. The undoped oxide film in the stack was a sacrificial layer whose thickness was defined as LG, the two phosphosilicate glass (PSG) layers were dopant sources used to form low-resistance, shallow, self-aligned S/D extension by SSD of phosphorus, and the thin nitride layers between the undoped oxide and the dopant sources functioned as etch stops and as precision offset spacers. A polysilicon source landing pad was deposited, implanted with arsenic, and patterned. After this landing pad and the top PSG dopant source had been encased in nitride via spacer formation, the sacrificial oxide layer was removed selectively to expose the vertical Si channel. A thin gate oxide was grown on the channel, and a phosphorous-doped, highly conformal a-Si gate was deposited and recrystallized. See Hergenrother et al. Page 3.6.1, Column 2.
Vertical field effect transistors may be fabricated, according to embodiments of the present invention by depositing a vertical channel on a microelectronic substrate at a thickness along the microelectronic substrate that is independent of lithography, the vertical channel extending orthogonal to the microelectronic substrate. Source and drain regions are formed at respective opposite ends of the vertical channel, and an insulated gate is formed adjacent the vertical channel.
By depositing a vertical channel that has a thickness that is independent of lithography, vertical field effect transistors according to embodiments of the invention may be scaled down independent of advances in photolithography. Moreover, the insulated gate may be formed by forming an insulated gate on the vertical channel, the insulated gate extending orthogonal to the microelectronic substrate and having a length along the channel that is independent of lithography, for example using vertical replacement gate formation techniques. Accordingly, both the channel thickness and the gate length of the FET may be controlled independent of lithography. Accordingly, relief from the technical barriers that may prevent the extension of fabrication technologies to their ultimate limit may be provided.
Other methods of fabricating vertical field effect transistors according to embodiments of the present invention, line a sidewall of a trench on a microelectronic substrate with a conformal silicon layer. The conformal silicon layer on the sidewall of the trench includes a first end portion adjacent the substrate, a second end portion remote from the substrate, and a middle portion between the first and second end portions. The first and second end portions are doped to form source and drain regions for the field effect transistor. A gate insulating layer is formed adjacent the middle portion and a gate electrode is formed on the gate insulating layer opposite the middle portion. Lining the sidewall of the trench may be performed by lining the sidewall of the trench with amorphous silicon and then crystallizing the amorphous silicon. After lining the sidewall, the trench that is lined may be plugged, using silicon dioxide, high dielectric constant dielectrics and/or other materials. In some embodiments, the entire sidewall of the trench may be lined with the conformal silicon layer, to provide a continuous conformal silicon layer. In other embodiments, spaced apart portions of the trench sidewall are lined to provide spaced apart conformal silicon plates.
In still other embodiments of the present invention, prior to lining the sidewall of the trench, a first doping layer is formed on the substrate, an intermediate layer is formed on the first doping layer opposite the substrate, and a second doping layer is formed on the intermediate layer opposite the first doping layer. The trench is defined in the first doping layer, the intermediate layer and the second doping layer. When lining the sidewall of the trench with the conformal silicon layer, the first end portion is adjacent the first doping layer, the second end portion is adjacent the second doping layer, and the middle portion is adjacent the intermediate layer. The first and second end portions are doped with dopants from the respective first and second doping layers adjacent thereto, to form the source and drain (or source/drain extension) regions for the field effect transistor. The doping layers may be any layers that can supply dopants to silicon. For example, doped and/or undoped phosphosilicate glass (PSG) and/or borosilicate glass (BSG) may be used. The gate insulating layer may be formed by removing the intermediate layer adjacent the middle portion, to expose at least some of the middle portion and forming a gate insulating layer on the middle portion that is exposed. The gate insulating layer may be formed by thermally oxidizing the middle portion that is exposed. The gate insulating layer also can be deposited using a conformal deposition technique, such as a CVD (Chemical Vapor Deposition) process.
Other methods of fabricating vertical field effect transistor according to embodiments of the present invention form a first doping layer on a microelectronic substrate, form an intermediate layer on the first doping layer opposite the substrate and form a second doping layer on the intermediate layer opposite the first doping layer. A trench is then formed in the first doping layer, the intermediate layer and the second doping layer, the trench including a trench sidewall. The trench sidewall is lined with a conformal amorphous silicon layer. The conformal silicon layer on the trench sidewall includes a first end portion adjacent the first doping layer, a second end portion adjacent the second doping layer, and a middle portion between the first and second end portions adjacent the intermediate layer. The amorphous silicon layer is then crystallized. The trench that is lined is plugged, for example, with silicon dioxide, high dielectric constant dielectrics and/or other materials. Annealing is performed to dope the first end portion and the second end portion with dopants from the first and second doping layers respectively. The intermediate layer is removed adjacent the middle portion to expose at least some of the middle portion. A gate insulating layer is formed on the middle portion that is exposed, and a gate electrode is formed on the gate insulating layer, opposite the middle portion. One or more drain contacts may be formed in the microelectronic substrate prior to forming the first doping layer. For example, silicide drain contacts may be formed. Moreover, one or more source contacts may be formed on the second end of the conformal silicon layer.
Vertical field effect transistors according to embodiments of the invention include a microelectronic substrate including a trench, wherein the trench defines a sidewall. A conformal monocrystalline silicon layer is included on the sidewall of the trench. The conformal monocrystalline silicon layer on the sidewall of the trench includes a drain region adjacent the substrate, a source region remote from the substrate, and a channel region between the source and drain regions. A plug is included in the trench that includes the conformal monocrystalline silicon layer on the sidewall thereof. The plug may comprise silicon dioxide, high dielectric constant materials and/or other materials. A gate insulating layer is included adjacent the channel, and a gate electrode is included on the gate insulating layer opposite the channel.
In some device embodiments, the conformal monocrystalline silicon layer on the sidewall of the trench is a continuous conformal monocrystalline silicon layer. In other embodiments, the conformal monocrystalline silicon layer comprises two or more spaced apart conformal portions on the sidewall of the trench.
Other field effect transistors according to embodiments of the invention can include a first layer on the substrate and a second layer on the first layer opposite the substrate. The trench extends in the doped layer and the second layer, and the gate insulating layer and the gate electrode are between the first and second layers. In some embodiments, the first and second layers comprise phosphosilicate glass. Accordingly, field effect transistors that can be scaled to nanoscale dimensions can be provided and can be manufactured using conventional processing steps.